Miniaturization of a nonvolatile semiconductor memory device such as an NAND flash memory in a longitudinal direction (a film thickness or the like) and a transverse direction (a wiring width, a space width, or the like) has been advanced with needs for high capacity.
As the miniaturization in the longitudinal direction, there is suggested a structure called lamination layer FG in which a floating gate (which will be appropriately referred to as “FG” hereinafter) is divided into two pieces, an equivalent oxide film thickness of a tunnel oxide film is divided into two, one of the two is arranged at the same position as a conventional tunnel oxide film, and the other is arranged at a position where the floating gate is divided into two pieces.
However, when simply shrinking an element in the miniaturization in the transverse direction is tried, there occurs a phenomenon called an inter-cell interference (Yupin/Enda) effect that a threshold value of a memory cell apparently increases due to a parasitic capacity between FGs that are adjacent to each other or a parasitic capacity between an FG and an active area (AA) that are adjacent to each other, and a breakthrough for such a limit has not been developed yet.